The present invention relates to a semiconductor device used to control high power and a drive method and drive apparatus.
Recently, IGBTs (Insulated Gate Bipolar Transistors) and IEGTs (Injection Enhanced Gate Transistors) have received a great deal of attention as power control semiconductor devices. These IGBT and IEGT are bipolar devices with MOS structures, and have the high-speed switching characteristics of the power MOSFET and the high-breakdown voltage, short-turn-on time characteristics of the bipolar transistor. For this reason, the IGBT and IEGT can be applied to power converters such as an inverter. The IGBT will be exemplified.
FIG. 1 is a circuit diagram showing the arrangement of a general inverter. High-side IGBT1 and low-side IGBT2, which respectively have reflux diodes D1 and D2 and gate resistances RG1 and RG2, are series-connected to a power supply voltage Vcc.
As for low-side IGBT2, a gate voltage of .+-.15V is applied to IGBT2 from a gate drive circuit (not shown) via the gate resistance RG2 to flow (ON) or cut off (OFF) a collector current Ic flowing through IGBT2 in correspondence with the gate signal. For example, if a positive gate signal is applied to a gate G of IGBT2, the collector current Ic flows to turn on IGBT2; if a negative gate signal is applied, the collector current Ic is cut off to turn off IGBT2.
When the gate signal changes from negative to positive, IGBT2 is turned on. IGBT2 shifts from the OFF state to the ON state to flow the collector current Ic. When the gate signal changes from positive to negative, IGBT2 is turned off. IGBT2 shifts from the ON state to the OFF state to cut off the collector current Ic.
FIG. 2 is a waveform chart showing an example of the turn-off waveform of the IGBT. FIG. 3 is a sectional view showing the structure of the IGBT for explaining turn-off operation. As shown in FIG. 3, the IGBT is constituted by forming a heavily doped p-type emitter layer 2 on one surface of a lightly doped n-type base layer 1 and forming a collector electrode 3 on the p-type emitter layer 2.
A p-type base layer 4 is selectively formed on the other surface of the n-type base layer 1, and a heavily doped n-type source layer 5 is formed on the surface of the p-type base layer 4. A gate electrode 7 is formed on the p-type base layer 4 between the n-type source and base layers 5 and 1 via a gate oxide film 6. An emitter electrode 8 is formed on the n-type source layer 5 and p-type base layer 4.
In this IGBT, if the gate signal supplied from the gate drive circuit changes from +15V to -15V, a gate voltage V.sub.G of IGBT2 connected to the gate drive circuit via the RB first falls to a given value (time t1) and keeps this value for a while (time t2). In this specification, this constant V.sub.G period (time t1 to t2) is called a mirror time in the MOSFET mode. During the mirror time in the MOSFET mode, a collector voltage V.sub.CE rises to about 15V.
After that, in the IGBT, a depletion layer having a high electric field starts extending from below the gate oxide film 6 and p-type base layer 4 into the n-type base layer 1, and the collector voltage V.sub.CE abruptly rises (from time t2). At the same time, the gate voltage V.sub.G starts gradually falling but is still higher than a threshold voltage Vth of the IBGT.
If the collector voltage is clamped by the diode, the collector current Ic is commutated to the diode (D1 in FIG. 1) and cut off. At the same time, the gate current also abruptly falls (time t3), and the gate voltage V.sub.G falls to the threshold voltage Vth or less (from time t3). In this specification, the period (time t2 to t3) required to reach the threshold voltage Vth of the IGBT after the gate voltage V.sub.G starts falling is called a mirror time in the IGBT mode.
This switching method is used in all current IGBTs. The switching method is advantageous in small drive force of the gate drive circuit and switching control-lability by the gate resistance RG. Particularly, this method is most easily, widely used in low-resistance, small-capacity IGBTs. Conventionally, RG is generally set large in order to stably operate devices such as the IGBT, which is adopted in all device applications at present.
However, the present inventors have studied to find that this switching method poses serious problems in stability upon switching. FIG. 3 shows carriers inside the device in the mirror time in the IGBT mode, in addition to the structure of the IGBT. Since the gate voltage V.sub.G is higher than the threshold voltage Vth, electrons are still injected (e- in FIG. 3), while holes flow from the collector side (h+ in FIG. 3). Thus, both holes and electrons exist in the high electric field (depletion layer). The presence of both holes and electrons degrades stability. Note that the broken line in FIG. 3 represents that the n-type base layer 1 above the broken line is in a high electric field and accumulated carriers remain in the n-type base layer 1 below the broken line.
For example, a space charge density .rho. in the high electric field is given by equation (1) using a donor density N.sub.D in the n-type base layer 1, a hole density p in the high electric field, and an electron density n in the high electric field:
.rho.=q(N.sub.D +p-n) (1)
A voltage applied to the IGBT is obtained by dividing the integrated value of the space charge density .rho. in the high electric field by a silicon permittivity .epsilon..sub.Si.
A current density J is given by equation (2) using an electronic current density Jn in the high electric field, a hole current density Jp in the high electric field, and a carrier saturation rate vs (about 10.sup.7 cm/s): EQU J=Jn+Jp=q.multidot.vs(p+n) (2)
In this case, it should be noted that holes and electrons have opposite charge polarities and cancel each other, i.e., are represented by the difference (p-n) as for the space charge density .rho., like equation (1), whereas holes and electrons have the same elementary electric charges and can be represented by the sum (p+n) of the hole and electron densities as for the current density J in the high electric field, like equation (2).
This shows that even if the electric field distribution inside the device keeps a constant value under conditions such as the collector voltage V.sub.CE, the current density is not determined in one-to-one correspondence but has a high degree of freedom, i.e., the current density cannot be made constant.
Further, if the collector voltage V.sub.CE and collector current Ic are positively fed back to the gate, the current density varies to make the stability of the current density J more unstable, and the current concentrates to destruct the device.
Next, various problems arising when the current capacity and breakdown voltage of one IGBT increase along with a larger capacity of the IGBT will be explained.
In recent years, since the current capacity of the IGBT increases, a plurality of IGBT chips are parallel-connected in one IGBT package (one device). For example, 4 to 6 chips are parallel-connected in the package for a 1,700-V, 400-A IGBT, about 6 chips are parallel-connected for a 2,000-V, 400-A IGBT, and 20 to 24 chips are parallel-connected for a 3.3-kV, 1,200-A IGBT. Each chip generally has a size of about 7 to 15 mm square. Connecting a larger number of chips increases the package size.
FIG. 4 is a circuit diagram showing the arrangement of IGBT1 and IGBT2 for two chips or devices that are parallel-connected. Gates G1 and G2 of the IGBT1 and IGBT2 are combined into one via corresponding gate resistances RG1 and RG2, and this gate is properly connected to a gate drive circuit via a resistance (not shown).
FIG. 5 shows the turn-off waveform of this circuit. The difference between the gate voltages V.sub.G1 and V.sub.G2 of the two IGBT1 and IGBT2 increases in the mirror time in the IGBT mode to make collector currents Ic1 and Ic2 greatly different and nonuniform between the two IGBT1 and IGBT2.
Such nonuniform current between the IGBT1 and IGBT2 does not pose any problem as far as one IGBT can cut off a double current. However, if a larger number of chips are parallel-connected, a current of several ten times compared to the ON state may flow upon switching one IGBT, and may destroy the device.
FIG. 6 schematically shows the carrier and electric field inside the device in the mirror time in the IGBT mode. Since the collector voltage VCE is shared in parallel connection, the two IGBT1 and IGBT2 have almost the same electric field distribution in the n-type base layer. Therefore, their space charge densities .rho. are substantially equal to each other, but the internal current densities J may become greatly different.
That is, although feedback from the collector flows electrons and holes in a large amount through one IGBT1 and in a small amount through the other IGBT2, the difference between the numbers of holes and electrons may be the same in IGBT1 and IGBT2.
Another example of the cause of nonuniform current is oscillation. FIG. 7 is a waveform chart showing an example of oscillation. In this phenomenon, even if the current becomes nonuniform between chips or parallel devices inside the package, no nonuniform current can be observed by measurement outside the package.
For this reason, the nonuniform current phenomenon has not been known so far. However, the present inventors have simulated to clear up the cause, as described above, and reproduces this phenomenon.
For example, the present inventors observed by simulation turn-off behavior in the arrangement in which the two IGBT1 and IGBT2 were parallel-connected, as shown in FIG. 8A. If 0.5-V very small spike noise 4 ns in width was mixed in the gate voltage of one IGBT2 250 ns after turn-off operation as shown in FIG. 8B, unbalance between the two IGBTs widened over time after 250 ns to generate nonuniform current and a oscillation phenomenon, as shown in FIG. 9.
Even if the application time of spike noise shifted to 150-ns time, nonuniform current and the oscillation phenomenon similarly appeared after 250 ns (the mirror time in the IGBT mode).
The same problem arises as not only nonuniform current in parallel connection but also nonuniform shared voltages V.sub.CE1 to V.sub.CEn upon switching when IGBT1 to IGBTn are series-connected, as shown in FIGS. 10 to 12.
As described above, the semiconductor device drive method suffers an unstable current density, current concentration, and the like for one IGBT (one chip).
When a plurality of IGBTs are parallel-connected, current concentration, the oscillation phenomenon, and the like occur to greatly degrade the device characteristics, and particularly, the cut-off current.
When a plurality of IGBTs are series-connected, the shared voltages become nonuniform.